A mod-W (or divide-by-N) asynchronous counter, where N=T, will count up to (N- 1) (an output of all 1’s) before resetting to all 0*s and beginning the count sequence again.
A general mod-N counter can be produced by using flip-flops with clear inputs and then simply decoding the Nth count state and using this to reset all flip-flops to zero. The count will therefore be from 0 to (TV-1) repeated since the circuit resets when the count gets to N. Note that because the Nth state must exist before it can be used to reset all of the flip-flops there is the likelihood that glitches will occur in some of the output lines during the resetting phase (since an output may go high as the reset count is reached, and then be reset to 0).
Design a mod-10 binary up-counter using negative edge JK flip-flops with active- LOW clear.
Four flip-flops are required, and decimal state 10 must be decoded and used to reset all flip-flops to give a repeated count from 0 to 9 (0000 to 1001)- State 10 is given by (1010) so a four-input NAND gate (as the clear is active-LOW) could be used to decode this count and clear all flip-flops. However, since states 11 to 15 will never be entered they can be considered as don’t care conditions and used to simplify the logic. From the Karnaugh map in Fig.7.2 it can be seen that the count state Q3Q1 can be used to perform the reset with the subsequent circuit also shown.
Asynchronous (ripple) counters are easy to design but, because the count has to ripple through the system, timing problems can occur and glitches can be generated. Consequently the speed of operation of this type of counter is limited.